Job Description

Senior Principal DFT Engineer

NXP’s Analog and Automotive Embedded Systems business line provides the processing power to help accelerate the next breakthrough automotive designs for advanced driver assistance systems, safety, secure care access, infotainment and in-vehicle networking. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly integrated, high performance, multi-domain devices compliant with the latest automotive and security standards.

As a DFT Engineer, you will be supporting new cutting-edge automotive microprocessor products as part of the product and test engineering “new production introduction” (NPI) team. Will interface with global and cross functional teams to improve DFT processes, methodologies, standards and quality that take product and test engineering into account. And will work closely with design teams to drive DFT innovative solutions.

Job Responsibilities:

• Embedded DFT post-Si lead in the Automotive Product and Test Engineering (PETE) group interfacing with DFT, Verification, Front-End, Physical Design FA and Product and Test engineering teams.
• Work in collaboration with cross functional teams to define new methodologies, processes, and standards with focus on quality.
• Be involved on our NPI’s from definitions stage through production launch stage.
• Responsible for helping resolve DFT related issues between PETE and DFT on our NPI’s.
• Assist test engineering with 1st silicon bring-up in regards to DFT.
• Drive innovative solution in our designs to improve testability and cost.
• Assist in defining our characterization and production scan flow standards.
• Support post-silicon activities, working with DFT, test engineering, product engineering, FA and validation teams.

Key Challenges:

• Improve development cycle time while maintaining high quality.
• Continuous improvement on way of working and establishing best practices.
• Meet customer PPM quality expectations for our automotive products.

Cross Functional Aspects:

• Working collaboratively to resolve DFT related issues on our devices and identify test coverage gaps between global design, verification, design-for-test (DFT), validation and product engineering teams.
• Interface with global teams in India, China and Malaysia.

Job Qualifications:

• BS/MS in Electrical/Electronics Engineering.
• Senior SoC DFT engineer with experiences in all aspects of DFT, including scan & ATPG, memory BIST, logic BIST, analog test, and post-silicon support.
• 10+ years of hands-on experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, ATPG.
• Strong expertise in DFT architectures, methodologies, and techniques, including scan insertion, ATPG algorithms, BIST Architectures, and JTAG on SOC devices.
• Experience with Siemens Tessent ATPG tools preferred.
• Experience with Siemen's Scan Streaming Network (SSN) highly desirable.
• Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design.
• Familiarity with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG).
• Scan Diagnostics experience highly desirable.
• Automated Test Equipment (ATE) knowledge and experience a plus.
• Identify new opportunities to innovate and improve quality and productivity in DFT and Product and Test community.
• Good team player with ability to work across functional teams, sites and cultures in issues resolution.
• Demonstrate good analysis and problem-solving skills.
• Self-motivated. Excellent written and verbal communication skill.

Job Location:

• Austin, TX. This is a hybrid role with 3 days in office and 2 days work from home. This is NOT open to being 100% remote.

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